This invention relates to ECL circuits and, in particular, to a low power ECL output gate.
A typical ECL output gate consists of a first and a second transistor which are differentially coupled such that their emitters are connected together and then coupled to a first supply voltage terminal by a current source. The bases of the first and second transistors are coupled to differential inputs at which a differential signal is typically applied thereto whereby the non-inverting signal is applied to the base of the first transistor while the inverting signal is applied to the base of the second transistor. The collectors of the first and second transistors are coupled to a second supply voltage terminal by first and second resistors, respectively. Further, the collector of the second transistor is coupled to the base of a third transistor, such that the third transistor is used to drive signals of typical ECL levels.
The aforedescribed configuration typically maintains a small value for the second resistor so that an adequate logic high voltage level (V.sub.OH) can be achieved when a logic high occurs at the base of the first transistor. However, when a logic low occurs at the base of the first transistor, the second resistor must provide an adequate voltage drop thereacross in order to achieve an adequate logic low voltage level (V.sub.OL). Therefore, since the second resistor is maintained small for adequate V.sub.OH levels, the current level provided by the current source must be made large so as to provide adequate V.sub.OL levels. Therefore, typical ECL output gates require a large amount of current for biasing which consequently forces the output gate to dissipate a large amount of power.
Hence, a need exists for an ECL output gate having lower power dissipation while still maintaining proper output voltage logic levels (V.sub.OL and V.sub.OH).
Accordingly, it is an object of the present invention to provide an improved ECL output gate.
Another object of the present invention is to provide an improved ECL output gate having reduced power dissipation.
Still another object of the present invention is to provide an improved ECL output gate having reduced power dissipation while still maintaining proper output voltage logic levels.
Yet another object of the present invention is to provide a circuit to vary the resistance of a resistor.
In carrying out the above and other object of the present invention, there is provided a BiMOS output gate comprising an input circuit responsive to logic input signals supplied to first and second inputs for providing output logic signals at first and second outputs; a field effect transistor having first and second electrodes and a control electrode, the control electrode being coupled to the first output of the input circuit, the first electrode being coupled to the second output of the input circuit, and the second electrode being coupled to a first supply voltage terminal; a first resistor coupled across the second and control electrodes of the field-effect transistor; a second resistor across the first and second electrodes of the field-effect transistor such that when the logic input signal applied to the first input of the input circuit is in a first logic state, the voltage drop occurring across the first resistor renders the field-effect transistor operative wherein the effective resistance of the second resistor is decreased; and an output circuit coupled to the second output of the input circuit for providing an output logic signal at an output terminal of the BiMOS output gate.
The above and other objects, features and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings.